How do you query the state of the interlock on the Model 7751 or 7752 modules in a Model 2790?
You cannot query the state of the interlock directly. However, there is a reliable indirect method of determining the state of the interlock. Also, you can detect an Interlock Violation using the instrument's status register system.
The best approach to check the state of the interlock at any time is to look at the state of Channel 20, which is the channel that switches the discharge resistors across the signal lines. Note: Channel 20 does not physically exist on a Model 7752 module, but the firmware behaves as if it does. As long as you do not close the channel in your application, it will always be open except when the 2790 automatically closes it. When everything is connected and operating normally, this channel only gets closed for brief (5 ms) intervals when the V-source is disconnected from the signal lines by opening Channel 22 or when a "ROUTE:OPEN:ALL" command is executed. However, if the interlock opens, Channel 20 closes and remains closed until the interlock is closed again and the channel is opened by either sending a "ROUTE:OPEN:ALL" command or, assuming the module is in Slot 1, a "ROUTE:MULTIPLE:OPEN (@120)" command. If the interlock is open, neither command will open Channel 20. With an open interlock, the "ROUTE:MULTIPLE:OPEN (@120)" command will generate a -224 "Illegal parameter value" error and not execute. The "ROUTE:OPEN:ALL" command will open all channels except 120 and it will NOT generate an error. Therefore, to check the state of the interlock at anytime without generating an error, send "ROUTE:OPEN:ALL" command and then either a "ROUTE:MULTIPLE:CLOSE?" or "ROUTE:MULTIPLE:CLOSE:STATE? (@120)" query. If the interlock is closed, the first query will return '"(@)", while the second query will return a zero (0). If the interlock is open, the first query will return '"(@120)", while the second query will return a one (1).
If you want to detect an event that corresponds to the opening of the interlock (Interlock Violation), you can check the Questionable Event Register. Bits 9 and 10 correspond to Interlock Violations for Slots 1 and 2, respectively. This is a latching register that holds conditions that appear on the Questionable Condition Register. If an open interlock is detected on power up or if a closed interlock opens, bit 9 or 10 will be set high depending on the slot the affected module is in. You can have the instrument generate a service request (GPIB SRQ) or you can simply read the register. To read the register, send a "STATUS:QUESTIONABLE?" query and enter the response. If only bit 9 (Slot 1 Interlock) is set, the number 512 will be returned. If only bit 10 is set, the number 1024 will be returned. If both 9 and 10 are set, the number 1536 will be returned. The issue with this approach is that as soon as you read the event register, you clear the bit(s). If an open interlock is closed and opened again, the bits will be set again. However, if an open interlock remains open, then after you read the register the first time and clear the bits, they will not be set high again.