Keithley Instruments Inc.

Parallel High Throughput WLR Testing for Advanced Gate Dielectrics

This presentation shows how to speed up testing of advanced gate dielectrics and why that’s needed as the industry approaches the 65nm node of the ITRS. The seminar details the challenges in wafer level reliability (WLR) testing, and provides solutions that improve both test integrity and throughput.

By viewing this presentation, you will learn about:

Issues associated with gate dielectric scaling
Mechanisms that degrade dielectric reliability
How failure mechanisms affect testing and sample size
Problems with conventional stress-measure methods for NBTI and TDDB
A new switchless parallel channel test method that provides better data and higher throughput while maintaining cost efficiency

This seminar is recommended for engineers, researchers, and scientists involved with traditional or compound semiconductors and associated material sciences who want a better understanding of WLR test technology.

Paul Meyer, Product Marketing Manager for Keithley Instruments presents the seminar.

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