Original broadcast date: April 22, 2008
This seminar is focused on examining the benefits and tradeoffs associated with parallel test solutions for wafer level reliability (WLR.) WLR tests are commonly used throughout the semiconductor lifecycle from technology development and process integration, to process reliability monitoring. The speed and accuracy of the WLR testing significantly impacts time to market for new designs. Parallel WLR testing provides a tool to significantly accelerate throughput by providing statistically significant samples sooner. Parallel WLR test solutions provide throughput benefits for both traditional and advance WLR measurements.
Participant Objectives:
By participating in this seminar, you will learn and understand:
- How to estimate speed and throughput impact of parallel WLR test on traditional reliability structures
- How to assess traditional test structures for use in a parallel test system
- The source of measurement errors that impact WLR measurements
- Typical configuration, measurement, and optimization techniques
Target Audience:
Engineers new to semiconductor reliability testing, test engineers who need to accelerate WLR testing, and QRA lab managers.
About the Presenter:
Paul Meyer is Senior Staff Technologist for Keithley Instruments’ Semiconductor Measurements Group, based in Cleveland, Ohio. Prior to joining Keithley, his career included equipment engineering in semiconductor fabs and semiconductor capital equipment manufacturers.
