WS/157: High Voltage Wafer Level Test - Tips, Tricks, and Pitfalls

WS/157: High Voltage Wafer Level Test - Tips, Tricks, and Pitfalls In this seminar, we will identify, discuss, and propose solutions for a number of challenges related to high voltage wafer level parametric test. Some key areas include:

High voltage probe card requirements
The risks of hot switching and cable charging
Protecting low voltage instruments during high voltage testing
High voltage parametric test roadmap

Target Audience:
This webinar is intended for test department engineers and managers in the semiconductor industry that are interested in learning more about the practical issues related to high voltage parametric test and characterization in a production environment.

About the Presenter
Paul Meyer is Senior Staff Technologist for Keithley Instruments’ Semiconductor Measurements Group, based in Cleveland, Ohio. Prior to joining Keithley, Paul’s career included designing semiconductor fab equipment, as well as equipment and equipment engineering in semiconductor fabs.

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