High-κ metal gate (HKMG) technology has highlighted the need to incorporate high-speed source/measurement testing into the physical and statistical modeling of intrinsic failure mechanisms that display time resolved phenomenon. Past reliability modeling test tools relied primarily on relatively slow DC semiconductor parametric analyzers and manual probing solutions. Today, failure mechanisms such as bias temperature instability (N-BTI and P-BTI) require high speed source and measure capability, such as pulse I/V, to resolve fast recovery affects. Also, the complexities of progressive breakdown in HKMG stacks require special techniques to induce arrested breakdown and capture fast transient events leading to hard breakdown. For the first time, the necessary capabilities are brought together in an integrate fully-automatic wafer prober control and test system architecture suitable for exploring advanced reliability measurements and correlating pulse techniques to more economic DC techniques while providing large statistical data sets.

Target Audience:
This seminar is recommended for those interested in leading edge scaled CMOS reliability challenges, Semiconductor Reliability Assurance managers and engineers, and advanced technology and process development engineers using newly introduced gate stack materials.

Speaker: Paul Meyer, Product Marketer in the Semi Labs group at Keithley Instruments, Inc.
Paul Meyer is a product marketer in the Semi Labs group at Keithley Instruments, Inc. in Cleveland. Previous experience includes production management, equipment development, and application engineering in the semiconductor industry. He earned his BSE degree from Missouri Institute of Technology.